DRAMs have become one of the most important of integrated circuit devices. The memory cell of a state of the art DRAM comprises a switch, generally an MOS transistor, and a storage capacitor, generally a trench capacitator. Memory cells of this kind in the millions are formed in a single chip of silicon and arranged in rows and columns. These are addressed by bit lines and word lines of auxiliary circuits that read in and read out binary digits (bits) stored in the capacitors.
The trend is to even higher and higher density of memory cells in a single chip. This requires that the cells be made smaller and smaller to permit higher and higher packing density. Typically, the memory cell of a DRAM uses for storage a capacitor that is formed by a polysilicon-filled trench that is isolated from the monocrystalline bulk of the chip by a dielectric layer that serves as the capacitor dielectric. The switch of the cell is formed by an MOS transistor in the monocrystalline bulk that has one of its current terminals, to be termed the drain, conductively connected to the polysilicon fill of the trench and the other, to be termed the source, connected to the bit line of the DRAM. Moreover, a recent innovation is to form the transistor as a vertical transistor located over the trench to save surface area of the silicon chip and so permit a higher packing density of cells in the chip.
One of the major problems posed by this kind of switching transistor is the need to form its most critical region, the base in which is formed the conductive channel when the transistor is closed, in essentially monocrystalline silicon, if the transistor is to have desired switching characteristics.
The present invention seeks to provide an improved solution to this problem.